1. Field of the Invention
The present patent specification relates to a single instruction, multiple data (SIMD) microprocessor, an image processing apparatus including same, and an image processing method used therein, and more particularly, to a SIMD microprocessor having multiple processor elements with multiple operation units, an image processing apparatus including the SIMD microprocessor, and an image processing method used in the SIMD microprocessor.
2. Discussion of the Background
A SIMD microprocessor sends a single instruction to multiple data to allow the multiple data to perform an identical action simultaneously. This architecture has now become widespread for use in operation of a large number of data with a single identical processing instruction, for example, image processing in a digital copier.
Such a SIMD microprocessor may include multiple processor elements or PEs, each including multiple operation units. In regular image processing, the SIMD-type processor generally aligns the multiple processor elements along a main scanning direction so as to have an identical action performed simultaneously on multiple data and achieve high-speed processing. Accordingly, the number of multiple processor elements included in the SIMD-type processor is one of most important elements to determine processing speed in image processing.
At the same time, there is increasing demand for ever higher image quality of images output from image processing apparatuses. Such improvement in performance relies significantly on bit width of operation data that is simultaneously processed in each processor element. That is, where a processing operation circuit and a data storage circuit included in a single processor element have a large bit width that can increase the accuracy of an operation, the quality of the output image can improve.
However, in terms of circuit unit size, there is a trade-off between an increase in the number of processor elements to increase operation speed and an increase in the bit widths of operation circuits and of data storage circuits to increase operation accuracy. Accordingly, it is important to appropriately analyze the contents of target image processing and construct a system to capable of performing such image processing properly.
One suggested approach is to have a SIMD-type processor including multiple operation circuits in each processor element so as to cause the multiple operation circuits to operate individually or cooperate with each other according to an operation condition. By so doing, the actual number of processor elements involved, and thus the bit width, can be changed.
Such a SIMD-type processor having the above-described configuration may have processor element (PE) numbers that are assigned in ascending order to each processor element, for example. Since each processor element includes multiple operation circuits, the relation between the PE number and the data unit of operation may depend on the configuration of the operation circuits. That is, some configurations of the operation circuits may not have a one-to-one relation between the PE number and the data unit of operation. The PE number is useful to designate specific image data, and therefore it is necessary that the relation between the PE number and the data unit of operation be 1:1.
Another approach is to have a SIMD-type processor having a different configuration to use a PE number assigned to each processor element for controlling the SIMD operation so that the operation can become more efficient. The PE number assigned to each processor element may be a fixed number.
Yet another approach is to have a SIMD-type processor having a configuration in which multiple processor elements are divided into several groups to share the use of hardware resources such as processor element local memories included in the groups so that the multiple processor elements can be effectively used as a whole processor. The SIMD-type processor having the above-described configuration may use a method for providing an identification code for designating a specific processor element within the multiple processor elements included in the groups. The identification codes may be provided to each group in an identical alignment. Therefore, an identical operation can be executed by the multiple processor elements in all groups having the identical identification code.
Further, yet another approach is to have a SIMD-type processor having a configuration in which each processor element is provided with an individual constant register for setting a unique value for the processor element from an external device. By using the individual constant register to control the SIMD operation, a unique operation may be performed by each processor element.